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1995 data sheet 8-bit single-chip microcontroller description the m pd780001 is a product of the 78k/0 series of microcontrollers, and features internal 8-bit resolution a/d converters, timers, serial interface units, interrupt controllers, and many other incorporated peripheral hardware. a one-time prom or eprom version ( m pd78p018f) and various development tools for the m pd780001 are available. the m pd78p018f is capable of operating in the same power supply voltage range as the m pd780001. functions are described in detail in the following users manuals. they should be read before starting design. m pd780001 users manual : in preparation 78k/0 series users manualinstruction : ieu-1372 features internal rom and ram internal rom : 8 kbytes internal high-speed ram : 192 bytes two types of packages are provided: 64-pin plastic shrink dip (750 mil) 64-pin plastic qfp (14 14 mm) instruction execution time can be varied from high-speed (0.4 m s) to low-speed (6.4 m s) i/o ports : 39 8-bit resolution a/d converter : 8 channels serial interface : 1 channel 3-wire serial i/o mode : 1 channel timer : 3 channels supply voltage : v dd = 2.7 to 5.5 v applications telephones, vcrs, audio equipment, cameras, air conditioners, home appliances, pagers, etc. ordering information part number package m pd780001cw-xxx 64-pin plastic shrink dip (750 mil) m pd780001gc-xxx-ab8 64-pin plastic qfp (14 14 mm) remark xxx indicates rom code suffix. the information in this document is subject to change without notice. m pd780001 mos integrated circuit document no. u10324ej1v0ds00 (1st edition) date published march 1996 p printed in japan the mark * shows major revised points.
2 m pd780001 78k/0 series development the following shows the 78k/0 series products development. subseries names are shown inside frames. * products in mass production products under development y subseries products are compatible with i 2 c bus. 100-pin 100-pin 80-pin 64-pin 64-pin 64-pin 64-pin 42-/44-pin pd78078 pd78070a pd78054 pd78018f pd78014 pd780001 pd78002 pd78083 m m m m m m m m pd78078y pd78070ay pd78054y pd78018fy pd78014y pd78002y m m m m m m 100-pin 80-pin 64-pin 100-pin 100-pin pd780208 pd78044a pd78024 m m m control fip tm drive pd78064b pd78064 m m lcd drive m pd78064y 80-pin pd78098 m iebus tm supported a timer was added to the pd78054 and external interface function was enhanced rom-less versions of the pd78078 uart and d/a converter were added to the pd78014 and i/o was enhanced low-voltage (1.8 v) operation versions of the pd78014 with several rom and ram capacities available an a/d converter and 16-bit timer were added to the pd78002 an a/d converter was added to the pd78002 basic subseries for control on-chip uart, capable of operating at a low voltage (1.8 v) the i/o and fip c/d of the pd78044a were enhanced, display output total: 53 a 6-bit u/d counter was added to the pd78024, display output total: 34 basic subseries for driving fip, display output total: 26 emi noise-reduced version of the pd78064 basic subseries for driving lcds, on-chip uart the iebus controller was added to the pd78054 m 78k/0 series m m m m m m m m m
3 m pd780001 the following table shows the differences among subseries functions. function rom timer 8-bit 8-bit serial interface i/o v dd min. external part number capacity 8-bit 16-bit watch wdt a/d d/a value expansion control m pd78078 32 k-60 k 4ch 1ch 1ch 1ch 8ch 2ch 3ch (uart: 1ch) 88 1.8 v available m pd78070a C 61 2.7 v m pd78054 16 k-60 k 2ch 69 2.0 v m pd78018f 8 k-60 k C 2ch 53 1.8 v m pd78014 8 k-32 k 2.7 v m pd780001 8 k C C 1ch 39 not available m pd78002 8 k-16 k 1ch C 53 available m pd78083 C 8ch 1ch (uart: 1ch) 33 1.8 v not available fip drive m pd780208 32 k-60 k 2ch 1ch 1ch 1ch 8ch C 2ch 74 2.7 v not available m pd78044a 16 k-40 k 68 m pd78024 24 k-32 k 54 lcd drive m pd78064b 32 k 2ch 1ch 1ch 1ch 8ch C 2ch (uart: 1ch) 57 2.0 v not available m pd78064 16 k-32 k iebus m pd78098 32 k-60 k 2ch 1ch 1ch 1ch 8ch 2ch 3ch (uart: 1ch) 69 2.7 v available supported
4 m pd780001 function description item function internal memory rom 8 kbytes internal high-speed 192 bytes ram memory space 64 kbytes general register 8 bits 32 registers (8 bits 8 registers 4 banks) instruction cycles instruction execution time variable function is integrated. 0.4 m s/0.8 m s/1.6 m s/3.2 m s/6.4 m s (@ 10.0 mhz operation with main system clock) instruction set ? 16-bit operation ? multiply/divide (8 bits 8 bits, 16 bits ? 8 bits) ? bit manipulate (set, reset, test, boolean operation) ? bcd adjust, etc. i/o ports total : 39 ? cmos input : 4 ? cmos input/output : 35 a/d converter ? 8-bit resolution 8 channels ? operable over a wide power supply voltage range: v dd = 2.7 to 5.5 v serial interface 3-wire serial i/o mode: 1 channel timer ? 8-bit timer/event counter: 2 channels ? watchdog timer: 1 channel timer output 2 clock output 39.1 khz, 78.1 khz, 156 khz, 313 khz, 625 khz, 1.25 mhz (@ 10.0 mhz operation with main system clock) buzzer output 2.4 khz, 4.9 khz, 9.8 khz (@ 10.0 mhz operation with main system clock) vectored maskable interrupts internal: 5, external: 3 interrupts non-maskable internal: 1 interrupt software interrupt internal: 1 test input external: 1 supply voltage v dd = 2.7 to 5.5 v operating ambient temperature t a = C40 to +85?c package ? 64-pin plastic shrink dip (750 mil) ? 64-pin plastic qfp (14 14 mm)
5 m pd780001 contents 1. pin configuration (top view) 6 2. block diagram 8 3. pin functions 9 3.1 port pins 9 3.2 non-port pins 10 3.3 pin i/o circuits and recommended connection of unused pins 11 4. memory space 13 5. peripheral hardware function features 14 5.1 ports 14 5.2 clock generator 15 5.3 timer/event counter 16 5.4 clock output control circuit 18 5.5 buzzer output control circuit 18 5.6 a/d converter 19 5.7 serial interface 20 6. interrupt functions and test function 21 6.1 interrupt functions 21 6.2 test function 23 7. standby functions 24 8. reset functions 24 9. instruction set 25 10. electrical specifications 27 11. package drawings 36 12. recommended soldering conditions 38 appendix a. development tools 39 appendix b. related documents 41 * *
6 m pd780001 1. pin configuration (top view) 64-pin plastic shrink dip (750 mil) m pd780001cw-xxx 1 p20/si1 2 p21/so1 3 p22/sck1 4 p23 5 p24 6 nc 7 nc 8 nc 9 p30 10 p31/to1 11 p32/to2 12 p33/ti1 13 p34/ti2 14 p35/pcl 15 p36/buz 16 p37 17 v ss 18 p40 19 p41 20 p42 21 p43 22 p44 23 p45 24 p46 25 p47 26 p50 27 p51 28 p52 29 p53 30 nc 31 p55 32 v ss 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 av ref av dd ani7 ani6 ani5 ani4 ani3 ani2 ani1 ani0 av ss nc nc ic x1 x2 v dd p03/intp3 p02/intp2 p01/intp1 nc reset p67 p66 p65 p64 p63 p62 p61 p60 p57 p56 cautions 1. always connect the ic (internally connected) pin to v ss directly. 2. always connect the nc (non-connection) pin to v ss (however, can also be left open). 3. always connect the av dd pin to v dd . 4. always connect the av ss pin to v ss .
7 m pd780001 64-pin plastic qfp (14 x 14 mm) m pd780001gc-xxx-ab8 cautions 1. always connect the ic (internally connected) pin to v ss directly. 2. always connect the nc (non-connection) pin to v ss (however, can also be left open). 3. always connect the av dd pin to v dd . 4. always connect the av ss pin to v ss . 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ani1 ani0 av ss nc nc ic x1 x2 v dd p03/intp3 p02/intp2 p01/intp1 nc reset p67 p66 p37 v ss p30 p31/to1 p32/to2 p33/ti1 p34/ti2 p35/pcl p36/buz p40 p41 p42 p43 p44 p45 p46 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 nc nc nc p24 p23 p22/sck1 p21/so1 p20/si1 av ref av dd ani7 ani6 ani5 ani4 ani3 ani2 p47 p50 p51 p52 p53 nc p55 v ss p56 p57 p60 p61 p62 p63 p64 p65
8 m pd780001 p01-p03 : port 0 p20-p24 : port 2 p30-p37 : port 3 p40-p47 : port 4 p50-p53, p55-p57 : port 5 p60-p67 : port 6 intp1-intp3 : interrupt from peripherals ti1, ti2 : timer input to1, to2 : timer output si1 : serial input so1 : serial output sck1 : serial clock pcl : programmable clock buz : buzzer clock x1, x2 : crystal reset : reset ani0-ani7 : analog input av dd : analog power supply av ss : analog ground av ref : analog reference voltage v dd : power supply v ss : ground ic : internally connected nc : non-connection 2. block diagram to1/p31 8-bit timer/ event counter 1 ti1/p33 to2/p32 8-bit timer/ event counter 2 ti2/p34 watchdog timer si1/p20 serial interface 1 so1/p21 sck1/p22 av dd a/d converter av ref ani0-ani7 interrupt control intp1/p01- intp3/p03 buzzer output buz/p36 clock output control pcl/p35 port 0 p01-p03 port 2 p20-p24 port 3 p30-p37 port 4 p40-p47 port 5 p50-p53, p55-p57 p60-p63 reset x1 x2 78k/0 cpu core rom (8 kbytes) ram (192 bytes) v dd v ss ic av ss p64-p67 port 6 system control
9 m pd780001 3. pin functions 3.1 port pins pin name i/o function after reset alternate function p01-p03 input/ port 0 input intp1- output 3-bit input/output port. intp3 input/output can be specified bit-wise. when used as an input port, pull-up resistor can be connected by software. p20 input/ port 2 input si1 p21 output 5-bit input/output port. so1 p22 input/output can be specified bit-wise. sck1 p23, 24 when used as an input port, pull-up resistor can be connected by software. p30 input/ port 3 input p31 output 8-bit input/output port. to1 p32 input/output can be specified bit-wise. to2 p33 when used as an input port, pull-up resistor can be connected by software. ti1 p34 ti2 p35 pcl p36 buz p37 p40-p47 input/ port 4 input output 8-bit input/output port. input/output can be specified in 8-bit units. when used as an input port, pull-up resistor can be connected by software. test input flag (krif) is set to 1 by falling edge detection. p50-p53, input/ port 5 input p55-p57 output 7-bit input/output port. leds can be driven directly. input/output can be specified bit-wise. when used as an input port, pull-up resistor can be connected by software. p60-p63 input port 6 input only. input p64-p67 input/ 8-bit input/output port. input/output can be specified bit-wise. input output when used as an input port, pull-up resistor can be connected by software.
10 m pd780001 pin name i/o function after reset alternate function intp1 input external interrupt input by which the effective edge (rising edge, falling edge, input p01 intp2 or both rising edge and falling edge) can be specified. p02 intp3 falling edge detection external interrupt input. p03 si1 input serial interface serial data input. input p20 so1 output serial interface serial data output. input p21 sck1 input/ serial interface serial clock input/output. input p22 output ti1 input external count clock input to 8-bit timer (tm1). input p33 ti2 external count clock input to 8-bit timer (tm2). p34 to1 output 8-bit timer output. input p31 to2 p32 pcl output clock output (for main system clock trimming). input p35 buz output buzzer output. input p36 ani0-ani7 input a/d converter analog input. input av ref input a/d converter reference voltage input. av dd a/d converter analog power supply. connected to v dd . av ss a/d converter ground potential. connected to v ss . reset input system reset input. x1 input main system clock oscillation crystal connection. x2 v dd positive power supply. v ss ground potential. ic internally connected. connected to v ss directly. nc not internally connected. connected to v ss (also can be left open). 3.2 non-port pins
11 m pd780001 3.3 pin i/o circuits and recommended connection of unused pins the input/output circuit type of each pin and recommended connection of unused pins are shown in table 3-1. for the input/output circuit configuration of each type, see figure 3-1. table 3-1. types of pin input/output circuit pin name input/output input/output recommended connection when not used circuit type p01/intp1 8-a input/output independently connected to v ss through resistor. p02/intp2 p03/intp3 ani0-ani7 7 input connected to v dd or v ss . p20/si1 8-a input/output independently connected to v dd or v ss through resistor. p21/so1 5-a p22/sck1 8-a p23 5-a p24 8-a p30 5-a p31/to1 p32/to2 p33/ti1 8-a p34/ti2 p35/pcl 5-a p36/buz p37 p40-p47 5-e input/output independently connected to v dd through resistor. p50-p53 5-a input/output independently connected to v dd or v ss through resistor. p55-p57 p60-p63 2-b input connected to v dd or v ss . p64-p67 5-a input/output independently connected to v dd or v ss through resistor. reset 2 input av ref connected to v ss . av dd connected to v dd . av ss connected to v ss . ic connected to v ss directly. nc connected to v ss (also can be left open). caution the connection of the nc pin differs from that of the prom version ( m pd78p018f).
12 m pd780001 type 2-b type 2 type 5-a type 5-e type 7 type 8-a figure 3-1. pin input/output circuits pullup enable data output disable v p-ch n-ch p-ch in/out dd v dd in schmitt-triggered input with hysteresis characteristic input enable in p-ch n-ch in pullup enable data output disable v p-ch p-ch in/out dd v dd v ref (threshold voltage) pullup enable data output disable v p-ch n-ch p-ch in/out dd v dd + input enable n-ch
13 m pd780001 4. memory space the memory map of the m pd780001 is shown in figure 4-1. figure 4-1. memory map ffffh ff00h feffh fe40h fe3fh fee0h fedfh 2000h 1fffh 0000h 1fffh 1000h 0fffh 0800h 07ffh 0080h 007fh 0040h 003fh 0000h special function registers (sfr) 256 x 8 bits general registers 32 x 8 bits internal high-speed ram 192 x 8 bits use prohibited program area callf entry area program area callt table area vector table area program memory space data memory space internal rom 8192 x 8 bits
14 m pd780001 5. peripheral hardware function features 5.1 ports the following two types of i/o ports are provided. cmos input (p60-p63) : 4 cmos input/output (port 0, port 2-port 5, p64-p67) : 35 total : 39 table 5-1. functions of ports port name pin name function port 0 p01-p03 input/output ports. input/output can be specified bit-wise. when used as an input port, on-chip pull-up resistor can be connected by software. port 2 p20-p24 input/output ports. input/output can be specified bit-wise. when used as an input port, on-chip pull-up resistor can be connected by software. port 3 p30-p37 input/output ports. input/output can be specified bit-wise. when used as an input port, on-chip pull-up resistor can be connected by software. port 4 p40-p47 input/output ports. input/output can be specified in 8-bit units. when used as an input port, on-chip pull-up resistor can be connected by software. test input flag (krif) is set to 1 by falling edge detection. port 5 p50-p53, input/output ports. input/output can be specified bit-wise. p55-p57 when used as an input port, on-chip pull-up resistor can be connected by software. leds can be driven directly. port 6 p60-p63 input-only port. p64-p67 input/output ports. input/output can be specified bit-wise. when used as an input port, on-chip pull-up resistor can be connected by software.
15 m pd780001 5.2 clock generator an on-chip main system clock generator is provided. the instruction exection time can be changed. 0.4 m s/0.8 m s/1.6 m s/3.2 m s/6.4 m s (main system clock: at 10.0-mhz operation) figure 5-1. clock generator block diagram selector main system clock oscillator prescaler prescaler f x 2 f x 2 2 f x 2 3 f x 2 4 standby control circuit clock to peripheral hardware cpu clock (f cpu ) stop f x x1 x2
16 m pd780001 5.3 timer/event counter the following three channels are incorporated in the timer/event counter. 8-bit timer/event counter : 2 channels watchdog timer : 1 channel table 5-2. types and functions of timer/event counter 8-bit timer/event watchdog counter timer type interval timer 2 channels 1 channel external event counter 2 channels e functions timer output 2 outputs e square wave output 2 outputs e interrupt request 2 1
17 m pd780001 internal bus 8-bit compare register (cr10) 8-bit timer register 1 (tm1) clear output control circuit output control circuit inttm1 to2/p32 inttm2 to1/p31 clear match selector 8-bit compare register (cr20) 8-bit timer register 2 (tm2) match internal bus selector selector selector selector f x /2 2 ? x /2 10 f x /2 12 ti1/p33 f x /2 2 ? x /2 10 f x /2 12 ti2/p34 figure 5-2. 8-bit timer/event counter block diagram figure 5-3. watchdog timer block diagram * fx 2 4 fx 2 5 fx 2 6 fx 2 7 fx 2 8 fx 2 9 fx 2 10 fx 2 12 control circuit 8-bit counter prescaler intwdt non-maskable interrupt request intwdt maskable interrupt request reset selector
18 m pd780001 5.4 clock output control circuit the clock with the following frequencies can be output for clock output. 39.1 khz/78.1 khz/156 khz/313 khz/625 khz/1.25 mhz (main system clock: at 10.0-mhz operation) figure 5-4. clock output control circuit block diagram 5.5 buzzer output control circuit a clock with the following frequencies can be output for buzzer output. 2.4 khz/4.9 khz/9.8 khz (main system clock: at 10.0-mhz operation) figure 5-5. buzzer output control circuit block diagram f x /2 10 f x /2 11 f x /2 12 selector output control circuit buz/p36 f x /2 3 f x /2 4 f x /2 5 f x /2 6 f x /2 7 f x /2 8 selector synchronization circuit output control circuit pcl/p35
19 m pd780001 5.6 a/d converter the a/d converter has on-chip eight 8-bit resolution channels. there are the following two methods to start a/d conversion. hardware starting software starting figure 5-6. a/d converter block diagram tap selector intad av dd intp3 internal bus av ref av ss a/d conversion result register (adcr) control circuit succesive approximation register (sar) falling edge detector ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 intp3/p03 selector sample & hold circuit voltage comparator series resistor string
20 m pd780001 5.7 serial interface one on-chip clocked serial interface is provided. serial interface channel 1 operates in msb/lsb-first switchable 3-wire serial i/o mode. figure 5-7. serial interface channel 1 block diagram internal bus interrupt request signal generator serial clock control circuit selector serial clock counter serial i/o shift register 1 (sio1) si1/p20 so1/p21 sck1/p22 intcsi1 f x /2 2 ?f x /2 9 to2
21 m pd780001 6. interrupt functions and test function 6.1 interrupt functions there are 10 interrupt functions of 3 different kinds as shown below. ? non-maskable interrupt : 1 ? maskable interrupts : 8 ? software interrupt : 1 table 6-1. interrupt source list interrupt default interrupt source internal/ vector table basic note 2 type priority note 1 name trigger external address configuration type non- intwdt watchdog timer overflow internal 0004h (a) maskable (with watchdog timer mode 1 selected) maskable 0 intwdt watchdog timer overflow (b) (with interval timer mode selected) 1 intp1 pin input edge detection external 0008h (c) 2 intp2 000ah 3 intp3 000ch 4 intcsi1 serial interface channel 1 transfer end internal 0010h (b) 5 inttm1 8-bit timer/event counter 1 match signal 0016h generation 6 inttm2 8-bit timer/event counter 2 match signal 0018h generation 7 intad a/d converter conversion end 001ah software brk brk instruction execution internal 003eh (d) notes 1. the default priority is the priority applicable when more than one maskable interrupt is generated. 0 is the highest priority and 7, the lowest. 2. basic configuration types (a) - (d) correspond to those on figure 6-1.
22 m pd780001 figure 6-1. interrupt function basic configuration (1/2) (a) internal non-maskable interrupt internal bus priority control circuit vector table address generator standby release signal interrupt request (b) internal maskable interrupt mk internal bus ie pr isp if priority control circuit vector table address generator standby release signal interrupt request (c) external maskable interrupt mk ie pr isp if priority control circuit vector table address generator external interrupt mode register (intm0) edge detector internal bus standby release signal interrupt request
23 m pd780001 figure 6-1. interrupt function basic configuration (2/2) (d) software interrupt priority control circuit vector table address generator internal bus interrupt request if : interrupt request flag ie : interrupt enable flag isp : in-service priority flag mk : interrupt mask flag pr : priority spcification flag 6.2 test function the following one test function is provided. test source internal/external name trigger intpt4 port 4 falling edge detection external mk internal bus if standby release signal test input signal figure 6-2. test function basic configuration if : test input flag mk : test mask flag
24 m pd780001 7. standby functions there are the following two standby functions to reduce the current consumption. ? halt mode : the cpu operating clock is stopped. the average current consumption can be reduced by intermittent operation in combination with the normal operating mode. ? stop mode : the main system clock oscillation is stopped. the whole operation by the main system clock is stopped, so that the system operates with ultra-low power dissipation. figure 7-1. standby functions main system clock operation stop mode (main system clock oscillation stopped) halt mode (clock supply to cpu is stopped, oscillation maintained) interrupt request interrupt request halt instruction stop instruction 8. reset functions there are the following two reset methods. ? external reset input by reset pin. ? internal reset by watchdog timer runaway time detection.
25 m pd780001 2nd operand #byte a r note sfr saddr !addr16 psw [de] [hl] [hl+ byte] $addr16 1 none [hl+b] 1st operand [hl+c] a add mov mov mov mov mov mov mov mov ror addc xch xch xch xch xch xch xch rol sub add add add add add rorc subc addc addc addc addc addc rolc and sub sub sub sub sub or subc subc subc subc subc xor and and and and and cmp or or or or or xor xor xor xor xor cmp cmp cmp cmp cmp r mov mov inc add dec addc sub subc and or xor cmp r1 dbnz sfr mov mov saddr mov mov dbnz inc add dec addc sub subc and or xor cmp !addr16 mov psw mov mov push pop [de] mov [hl] mov ror4 rol4 [hl+byte] mov [hl+b] [hl+c] x mulu c divuw 9. instruction set (1) 8-bit instruction mov, xch, add, addc, sub, subc, and, or, xor, cmp, mulu, divuw, inc, dec, ror, rol, rorc, rolc, ror4, rol4, push, pop, dbnz note except r=a
26 m pd780001 2nd operand #word ax rp note sfrp saddrp !addr16 sp none 1st operand ax addw movw movw movw movw movw subw xchw cmpw rp movw movw note incw, decw push, pop sfrp movw movw saddrp movw movw !addr16 movw sp movw movw (2) 16-bit instruction movw, xchw, addw, subw, cmpw, push, pop, incw, decw note only when rp=bc, de, hl. (3) bit manipulation instruction mov1, and1, or1, xor1, set1, clr1, not1, bt, bf, btclr 2nd operand a.bit sfr.bit saddr.bit psw.bit [hl].bit cy $addr16 none 1st operand a.bit mov1 bt set1 bf clr1 btclr sfr.bit mov1 bt set1 bf clr1 btclr saddr.bit mov1 bt set1 bf clr1 btclr psw.bit mov1 bt set1 bf clr1 btclr [hl].bit mov1 bt set1 bf clr1 btclr cy mov1 mov1 mov1 mov1 mov1 set1 and1 and1 and1 and1 and1 clr1 or1 or1 or1 or1 or1 not1 xor1 xor1 xor1 xor1 xor1 (4) call instruction/branch instruction call, callf, callt, br, bc, bnc, bz, bnz, bt, bf, btclr, dbnz (5) other instruction adjba, adjbs, brk, ret, reti, retb, sel, nop, ei, di, halt, stop 2nd operand ax !addr16 !addr11 [addr5] $addr16 1st operand basic instruction br call, br callf callt br, bc, bnc, bz, bnz compound instruction bt, bf, btclr, dbnz
27 m pd780001 parameter symbol test conditions ratings unit supply voltage v dd C0.3 to +7.0 v av dd C0.3 to v dd +0.3 v av ref C0.3 to v dd +0.3 v av ss C0.3 to +0.3 v input voltage v i p01-p03, p20-p24, p30-p37, p40-p47, C0.3 to v dd +0.3 v p50-p53, p55-p57, p60-p67, x1, x2 output voltage v o C0.3 to v dd +0.3 v analog input voltage v an ani0-ani7 analog input pins av ss C 0.3 to av ref + 0.3 v output current, high i oh per pin C10 ma total for p20-p24, p30-p37 C15 ma total for p01-p03, p40-p47, p50-p53, p55-p57, C15 ma p64-p67 output current, low i ol note per pin peak value 30 ma r.m.s. value 15 ma total for p40-p47, p50-p53, p55 peak value 100 ma r.m.s. value 70 ma total for p01-p03, p56, p57, peak value 100 ma p64-p67 r.m.s. value 70 ma total for p01-p03, p64-p67 peak value 50 ma r.m.s. value 20 ma total for p20-p24, p30-p37 peak value 50 ma r.m.s. value 20 ma operating ambient temperature t a C40 to +85 c storage temperature t opt C65 to +150 c 10. electrical specifications absolute maximum ratings (t a = 25 c) note the r.m.s. value should be calculated as follows: [r.m.s. value] = [peak value] duty caution exposure to absolute maximum ratings for extended periods may affect device reliability; exceeding the ratings could cause permanent damage. the parameters apply independently. the device should be operated within the limits specified. capacitance (t a = 25 c, v dd = v ss = 0 v) parameter symbol test conditions min. typ. max. unit input capacitance c in f = 1 mhz, unmeasured pins returned to 0 v. 15 pf i/o capacitance c io f = 1 mhz, p01-p03, p20-p24, p30-p37, 15 pf unmeasured pins p40-p47, p50-p53, p55-p57, returned to 0 v. p64-p67 remark unless otherwise specified, dual-function pin characteristics are the same as port pin characteristics. *
28 m pd780001 resonator recommended parameter test conditions min. typ. max. unit circuit ceramic oscillation frequency v dd = oscillation voltage 1 10 mhz resonator (f x ) note 1 range oscillation stabilization after v dd came to min. 4 ms time note 2 of oscillation voltage range crystal oscillation frequency 1 8.38 10 mhz resonator (f x ) note 1 oscillation stabilization v dd = 4.5 to 5.5 v 10 ms time note 2 30 external clock x1 input frequency 1.0 10.0 mhz (f x ) note 1 x1 input high- and 42.5 500 ns low-level widths (t xh , t xl ) main system clock oscillator characteristics (t a = C40 to +85 c, v dd = 2.7 to 5.5 v) x1 x2 c1 c2 v ss notes 1. only the oscillator characteristics are shown. for the instruction execution time, refer to ac characteristics. 2. time required for oscillation to stabilize after a reset or the stop mode has been released. caution when using the oscillation circuit of the main system clock, wire the portion enclosed in dotted lines in the figures as follows to avoid adverse influences on the wiring capacitance: ? keep the wiring length as short as possible. ? do not cross the wiring over other signal lines. ? do not route the wiring in the vicinity of lines through which a high fluctuating current flows. ? always keep the ground point of the capacitor of the oscillation circuit at the same potential as v ss . ? do not connect the power source to a ground pattern through which a high current flows. ? do not extract signals from the oscillation circuit. x1 x2 c1 c2 r1 v ss x1 x2 pd74hcu04 m
29 m pd780001 parameter symbol test conditions min. typ. max. unit input voltage, high v ih1 p21, p23, p30-p32, p35-p37, p40-p47, 0.7v dd v dd v p50-p53, p55-57, p60-p67 v ih2 p01-p03, p20, p22, p24, p33, p34, reset 0.8v dd v dd v v ih3 x1, x2 v dd C0.5 v dd v input voltage, low v il1 p21, p23, p30-p32, p35-p37, p40-p47, 0 0.3v dd v p50-p53, p55-p57, p60-p67 v il2 p01-p03, p20, p22, p24, p33, p34, reset 0 0.2v dd v v il3 x1, x2 0 0.4 v output voltage, high v oh v dd = 4.5 to 5.5 v, i oh = C1 ma v dd C1.0 v i oh = C100 m av dd C0.5 v output voltage, low v ol1 p50-p53, p55-p57 v dd = 4.5 to 5.5 v, i oh = 15 ma 0.4 2.0 v p01-p03, p20-24, v dd = 4.5 to 5.5 v, i oh = 1.6 ma 0.4 v p30-p37, p40-p47, p64-p67 v ol2 i ol = 400 m a 0.5 v input leakage i lh1 v in = v dd p01-p03, p20-24, p30-p37, 3 m a current, high p40-p47, p50-p53, p55-p57, p60-p67, ani0-ani7, reset i lh2 x1, x2 20 m a input leakage i lil1 v in = 0 v p01-p03, p20-24, p30-p37, C3 m a current, low p40-p47, p50-p53, p55-p57, p60-p67, ani0-ani7, reset i lil2 x1, x2 C20 m a output leakage i loh v out = v dd 3 m a current, high output leakage i lol v out = 0 v C3 m a current, low software pull-up r v in = 0 v, 4.5 v dd 5.5 v 15 40 90 k w resistance p20-p24, p30-p37, p40-p47, p50-p53, 2.7 v dd < 4.5 v 20 500 k w p55-p57, p64-p67 dc characteristics (t a = C40 to +85 c, v dd = 2.7 to 5.5 v) remark unless otherwise specified, dual-function pin characteristics are the same as port pin characteristics.
30 m pd780001 parameter symbol test conditions min. typ. max. unit supply current note 1 i dd1 8.38-mhz crystal oscil- v dd = 5.0 v 10% note 2 6.5 19.5 ma lation operating mode v dd = 3.0 v 10% note 3 0.7 2.1 ma i dd2 8.38-mhz crystal oscil- v dd = 5.0 v 10% 1.4 4.2 ma lation halt mode v dd = 3.0 v 10% 550 1650 m a i dd3 stop mode v dd = 5.0 v 10% 0.1 20 m a v dd = 3.0 v 10% 0.05 10 m a dc characteristics (t a = C40 to +85 c, v dd = 2.7 to 5.5 v) notes 1. not including av ref current and port current. 2. high-speed mode operation (when processor clock control register (pcc) is set to 00h). 3. low-speed mode operation (when pcc is set to 04h). remark unless otherwise specified, dual-function pin characteristics are the same as port pin characteristics.
31 m pd780001 ac characteristics (t a = C40 to +85 c, v dd = 2.7 to 5.5 v) (1) basic operation parameter symbol test conditions min. typ. max. unit cycle time t cy v dd = 4.5 to 5.5 v 0.4 64 m s (minimum instruction execution 0.96 64 m s time) ti1, ti2 input frequency f ti v dd = 4.5 to 5.5 v 0 4 mhz 0 275 khz ti1, ti2 input t tih ,v dd = 4.5 to 5.5 v 100 ns high-/low-level width t til 1.8 m s interrupt input t inth , intp1-intp3 10 m s high-/low-level width t intl kr0-kr7 10 m s reset low-level width t rsl 10 m s m pd780001 m pd78p018f (reference) t cy vs v dd (main system clock operation) t cy vs v dd (main system clock operation) caution the operation guaranteed range of the m pd780001 is different from that of the m pd78p018f. 60 10 2.0 1.0 1 023456 0.5 0.4 60 10 2.0 1.0 1 023456 0.5 0.4 cycle time t cy [ s] power supply voltage v dd [v] power supply voltage v dd [v] m cycle time t cy [ s] m operation guaranteed range operation guaranteed range
32 m pd780001 (2) serial interface (t a = e40 to +85 ?c, v dd = 2.7 to 5.5 v) (a) 3-wire serial i/o mode (sck1 ... internal clock output) parameter symbol test conditions min. typ. max. unit sck1 cycle time t kcy1 v dd = 4.5 to 5.5 v 800 ns 1600 ns sck1 high-/low-level width t kh1 ,v dd = 4.5 to 5.5 v t kcy1 /2C50 ns t kl1 100 ns si1 setup time t sik1 v dd = 4.5 to 5.5 v 100 ns (to sck1 - ) 150 ns si1 hold time t ksi1 400 ns (from sck1 - ) sck1 ? so1 t kso1 c = 100 pf note 300 ns output delay time note c is the so1 output line load capacitance. (b) 3-wire serial i/o mode (sck1 ... external clock input) parameter symbol test conditions min. typ. max. unit sck1 cycle time t kcy2 v dd = 4.5 to 5.5 v 800 ns 1600 ns sck1 high-/low-level width t kh2 ,v dd = 4.5 to 5.5 v 400 ns t kl2 800 ns si1 setup time t sik2 100 ns (to sck1 - ) ns si1 hold time (from sck1 - )t ksi2 400 ns sck1 ? so1 t kso2 c = 100 pf note 300 ns output delay time sck1 rise, fall time t r , t f v dd = 4.5 to 5.5 v 1000 ns note c is the so1 output line load capacitance.
33 m pd780001 ac timing test point (excluding x1 input) 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd test points ti timing clock timing serial transfer timing 3-wire serial i/o mode: t kcy1, 2 t kl1, 2 t r t f t kh1, 2 sck1 si1 so1 t sik1, 2 t ksi1, 2 t kso1, 2 input data output data t xl t xh 1/f x v dd ?0.5 v 0.4 v t til t tih 1/f ti x1 input ti1, ti2
34 m pd780001 a/d converter characteristics (t a = C40 to +85 c, av dd = v dd = 4.2 to 5.5 v, av ss = v ss = 0 v) (t a = C10 to +85 c, av dd = v dd = 4.0 to 5.5 v, av ss = v ss = 0 v) parameter symbol test conditions min. typ. max. unit resolution 888bit total error note 0.6 % conversion time t conv 19.1 200 m s sampling time t samp 24/f x m s analog input voltage v ian av ss av ref v reference voltage av ref 2.7 av dd v av ref -av ss resistance r airef 414 k w note excluding quantization error ( 1/2 lsb). shown as a percentage of the full scale value. data memory stop mode low supply voltage data retention characteristics (t a = C40 to +85 c) parameter symbol test conditions min. typ. max. unit data retention supply voltage v dddr 2.0 5.5 v data retention supply current i dddr v dddr = 2.0 v 0.1 10 m a release signal setup time t srel 0 m s oscillation stabilization wait t wait release by reset 2 18 /f x ms time release by interrupt note ms note 2 13 /f x or 2 15 /f x -2 18 /f x can be selected by bit 0-bit 2 (osts0-osts2) of oscillation stabilization time selection register (osts). data retention timing (stop mode released by reset) t srel t wait v dd reset stop instruction execution stop mode data retention mode internal reset operation halt mode operating mode v dddr
35 m pd780001 data retention timing (standby release signal: stop mode released by interrupt signal) t srel t wait v dd stop instruction execution stop mode data retention mode halt mode operating mode standby release signal (interrupt request) v dddr interrupt input timing reset input timing t rsl reset t intl t inth t intl intp3 intp1, intp2
36 m pd780001 11. package drawings remark the shape and material of the es product is the same as those of the mass-produced product. a i j g h f d n m c b m r 64 33 32 1 k l note each lead centerline is located within 0.17 mm (0.007 inch) of its true position (t.p.) at maximum material condition. p64c-70-750a,c-1 item millimeters inches a b c d f g h i j k 58.68 max. 1.778 (t.p.) 3.2?.3 0.51 min. 4.31 max. 1.78 max. l m 0.17 0.25 19.05 (t.p.) 5.08 max. 17.0 n 0~15 0.50?.10 0.9 min. r 2.311 max. 0.070 max. 0.020 0.035 min. 0.126?.012 0.020 min. 0.170 max. 0.200 max. 0.750 (t.p.) 0.669 0.010 0.007 0~15 +0.004 ?.003 0.070 (t.p.) 1) item "k" to center of leads when formed parallel. 2) +0.10 ?.05 +0.004 ?.005 64 pin plastic shrink dip (750 mil)
37 m pd780001 remark the shape and material of the es product is the same as those of the mass-produced product. n a m f b 48 49 32 k l 64 1 17 16 33 d c detail of lead end s q 55 p m i h j g p64gc-80-ab8-3 item millimeters inches a b c d f g h i j k l 17.6 0.4 14.0 0.2 1.0 0.35 0.10 0.15 14.0 0.2 0.693 0.016 0.039 0.039 0.006 0.031 (t.p.) 0.551 note m n 0.10 0.15 1.8 0.2 0.8 (t.p.) 0.004 0.006 +0.004 0.003 each lead centerline is located within 0.15 mm (0.006 inch) of its true position (t.p.) at maximum material condition. 0.071 0.008 0.014 0.551 0.8 0.2 0.031 p 2.55 0.100 0.693 0.016 17.6 0.4 1.0 +0.009 0.008 q 0.1 0.1 0.004 0.004 s 2.85 max. 0.112 max. +0.10 0.05 +0.009 0.008 +0.004 0.005 +0.009 0.008 64 pin plastic qfp ( 14)
38 m pd780001 soldering method soldering conditions symbol infrared ray reflow package peak temperature: 235?c, time: 30 seconds max. (210?c min.), ir35-00-2 number of times: 2 max. < cautions > (1) wait for the device temperature to return to normal after the first reflow before starting the second reflow. (2) do not perform flux cleaning with water after the first reflow. vps package peak temperature: 215?c, time: 40 seconds max. (200?c min.), vp15-00-2 number of times: 2 max. < cautions > (1) wait for the device temperature to return to normal after the first reflow before starting the second reflow. (2) do not perform flux cleaning with water after the first reflow. wave soldering solder temperature: 260?c max., time: 10 seconds max., ws60-00-1 number of times: 1, preheating temperature: 120 c max. (package surface temperature) partial heating pin temperature: 300?c max. time: 3 seconds max. (per device side) 12. recommended soldering conditions it is recommended that the m pd780001 be soldered under the following conditions. for details on the recommended soldering conditions, refer to information document "semiconductor device mounting technology manual" (iei-1207) . for soldering methods and conditions other than those recommended, please contact an nec sales representative. table 12-1. surface mount type soldering conditions m pd780001gc-xxx-ab8: 64-pin plastic qfp (14 14 mm) * caution do not use different soldering methods together (except for partial heating method). table 12-2. through-hole type soldering conditions m pd780001cw-xxx: 64-pin plastic shrink dip (750 mil) soldering method soldering conditions wave soldering solder temperature: 260?c max., time: 10 seconds max. (pin only) partial heating pin temperature: 300?c max., time: 3 seconds max. (per pin) caution apply wave soldering only to the pins and be careful so as not to bring solder into direct contact with the package.
39 m pd780001 appendix a. development tools the following development tools are available for system development using the m pd780001. language processing software ra78k/0 notes 1, 2, 3 assembler package common to the 78k/0 series cc78k/0 notes 1, 2, 3 c compiler package common to the 78k/0 series df780001 notes 1, 2, 3 m pd780001 device file cc78k/0-l notes 1, 2, 3 c compiler library source file common to the 78k/0 series prom writing tools pg-1500 prom programmer pa-78p018cw programmer adapter connected to the pg-1500 pa-78p018gc pa-78p018kk-s pg-1500 controller notes 1, 2 control program used for the pg-1500 debugging tools ie-78000-r in-circuit emulator common to the 78k/0 series ie-78000-r-bk break board common to the 78k/0 series ie-78014-r-em-a emulation board common to the m pd78018f subseries, etc. ep-78240cw-r emulation probe common to the m pd78244 subseries ep-78240gc-r ev-9200gc-64 socket to be mounted on user system board created for the 64-pin plastic qfp sm78k0 notes 4, 5 system simulator common to the 78k/0 series sd78k/0 notes 1, 2 ie-78000-r screen debugger df780001 notes 1, 2, 4, 5 m pd780001 device file real-time os mx78k0 notes 1, 2, 3 78k/0 series os * *
40 m pd780001 fuzzy inference development support system fe9000 note 1 /fe9200 note 5 fuzzy knowledge data creation tool ft9080 note 1 /ft9085 note 2 translator fi78k0 notes 1, 2 fuzzy inference module fd78k0 notes 1, 2 fuzzy inference debugger notes 1. based on pc-9800 series (ms-dos tm ) 2. based on ibm pc/at tm (pc dos tm ) 3. based on hp9000 series 300 tm , hp9000 series 700 tm (hp-ux tm ), sparcstation tm (sunos tm ), and ews-4800 series (ews-ux/v) 4. based on pc-9800 series (ms-dos + windows tm ) 5. based on ibm pc/at (pc dos + windows) remark ra78k/0, cc78k/0, sm78k0, and sd78k/0 are used in combination with the df780001.
41 m pd780001 appendix b. related documents documents related to devices document name document no. japanese english m pd780001 users manual in preparation planned 78k/0 series users manualinstructions ieu-849 ieu-1372 78k/0 series instruction table iem-5522 78k/0 series instruction set iem-5521 m pd780001 special function register table planned documents related to development tools (user's manual) document name document no. japanese english ra78k series assembler package operation eeu-809 eeu-1399 language eeu-815 eeu-1404 ra78k series structured assembler preprocessor eeu-817 eeu-1402 cc78k series c compiler operation eeu-656 eeu-1280 language eeu-655 eeu-1284 cc78k/0 c compiler application note programming eea-618 planned know-how cc78k series library source file eeu-777 pg-1500 prom programmer eeu-651 eeu-1335 pg-1500 controller pc-9800 series (ms-dos) based eeu-704 planned pg-1500 controller ibm pc series (pc dos) based eeu-5008 eeu-1291 ie-78000-r eeu-810 eeu-1398 ie-78000-r-bk eeu-867 eeu-1427 ie-78014-r-em-a eeu-962 eeu-1487 ep-78240 eeu-986 eeu-1513 sm78k0 system simulator reference eeu-5002 planned sm78k series system simulator external parts user u10092j planned open interface specification sd78k/0 screen debugger introduction eeu-852 pc-9800 series (ms-dos) based reference eeu-816 sd78k/0 screen debugger introduction eeu-5024 eeu-1414 ibm pc/at (pc dos) based reference eeu-993 eeu-1413 caution the contents of the documents listed above are subject to change without prior notice. make sure to use the latest edition when starting design. * *
42 m pd780001 documents related to embedded software (user?s manual) document name document no. japanese english 78k/0 series os mx78k0 basic eeu-5010 fuzzy knowledge data creation tool eeu-829 eeu-1438 78k/0, 78k/ii, and 87ad series fuzzy inference development support systemCtranslator eeu-862 eeu-1444 78k/0 series fuzzy inference development support system fuzzy inference module eeu-858 eeu-1441 78k/0 series fuzzy inference development support system fuzzy inference debugger eeu-921 eeu-1458 other documents document name document no. japanese english semiconductor package manual iei-635 iei-1213 semiconductor device mounting technology manual iei-616 iei-1207 quality grades on nec semiconductor devices iei-620 iei-1209 nec semiconductor device reliability/quality control system iem-5068 electrostatic discharge (esd) test mem-539 guide to quality assurance for semiconductor devices mei-603 mei-1202 microcontroller-related product guide C third party products C mei-604 caution the contents of the documents listed above are subject to change without prior notice. be sure to use the latest edition when starting design.
43 m pd780001 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and trans- ported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. fip and iebus are trademarks of nec corporation. ms-dos and windows are trademarks of microsoft corporation. pc/at and pc dos are trademarks of ibm corporation. hp9000 series 300, hp9000 series 700, and hp-ux are trademarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. sunos is a trademark of sun microsystems, inc.
m pd780001 m4 94.11 no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customer must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: standard, special, and specific. the specific quality grade applies only to devices developed based on a customer designated quality assurance program for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices in standard unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact nec sales representative in advance. anti-radioactive design is not implemented in this product. the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. the export of this product from japan is regulated by the japanese government. to export this product may be prohibited withou t governmental license, the need for which must be judged by the customer. the export or re-export of this product from a countr y other than japan may also be prohibited without a license from that country. please call an nec sales representative.

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